It is desired to determine the effect of package style on the number of circuits (logic gates) that can\nbe fabricated onto an IC chip to which the pac
It is desired to determine the effect of package style on the number of circuits (logic gates) that can
\r\nbe fabricated onto an IC chip to which the package is assembled. Using Rent's rule with C = 4.5 and
\r\nm = 0.5, compute the estimated number of devices (logic gates) that could be placed on the chip in
\r\nthe following cases: (a) a DIP with 16 I/O pins on a side - a total of 32 pins; (b) a square chip carrierwith 16 pins on a side - a total of 64 I/O pins; and (c) a pin grid array with 16 by 16 pins - a total of
\r\n256 pins